1. Field of the Invention
The present invention relates to a capacitor charging control circuit which evenly charges plural series-connected capacitors.
2. Description of the Related Art
An electrical double layer capacitor can rapidly charged, while it takes a long time to charge a secondary battery. Additionally, the electrical double layer capacitor has the feature not shared by the secondary battery. That is, a large amount of energy can be stored (high energy density) in the electrical double layer capacitor. However, because the electrical double layer capacitor has a low rated voltage of about 3.0V, usually the plural electrical double layer capacitors are connected in series to ensure a large voltage.
In charging the large-capacity capacitor in which the plural electrical double layer capacitors are connected in series, uneven charging voltages are generated in the capacitors due to a difference in capacity among the electrical double layer capacitors, self-charging, and self-discharge.
Usually a charging uniformizing circuit called a parallel monitor circuit is used as the measure against the uneven charging voltages. For example, in a capacitor charging monitor and control apparatus disclosed in Japanese Patent No 3313647, parallel monitor circuits are provided in series-connected electrical double layer capacitors respectively, a charging current of the electrical double layer capacitor is bypassed by a bypass transistor of the parallel monitor circuit when a voltage at the electrical double layer capacitor (voltage between both ends of the electrical double layer capacitor) reaches a predetermined monitor voltage, whereby the voltage at the electrical double layer capacitor is maintained at a predetermined monitor voltage value. In the beginning of the charging, initialization is performed by tentatively uniformizing the voltages at the electrical double layer capacitors to the monitor voltage, and the electrical double layer capacitors are fully charged after the voltages at the electrical double layer capacitors are uniformized to the predetermined monitor voltage, whereby a variation in charging is reduced during in fully charging the capacitors.
However, in the parallel monitor circuit disclosed in Japanese Patent No. 3313647, control cannot finely be performed according to various conditions due to the one monitor voltage during the initialization. Therefore, there is the large variation in the charged state of the capacitors, when fully charging is detected to stop the charging.
Therefore, in a parallel monitor circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155, the monitor voltages are set in plural stages, the monitor voltages of the electrical double layer capacitors are uniformized by charging the electrical double layer capacitors to a larger monitor voltage when the voltages of the electrical double layer capacitors are uniformized to a certain monitor voltage, and the electrical double layer capacitors are charged up to the fully charging voltage while the voltages of the electrical double layer capacitors are gradually uniformized to a larger monitor voltage.
FIG. 1 is a circuit diagram showing a monitor voltage producing circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155. In the monitor voltage producing circuit, bypass transistors Q1, Q2, . . . whose emitters are connected to resistors R1, R2, . . . are connected to electrical double layer capacitors (hereinafter simply referred to as capacitor) C1, C2, . . . in parallel, and a power supply Vdd is connected to the capacitor C1. Portion surrounded by broken lines constitute parallel monitor circuits PM1, PM2, . . . of the capacitors C1, C2, . . . . Because the parallel monitor circuits PM1, PM2, . . . have the same configuration, the parallel monitor circuit PM1 will be described below.
The parallel monitor circuit PM1 includes a voltage setting circuit VS1, a comparator CMP11, a comparator CMP12, a reference voltage Vr1, an output control circuit OC1, and a bypass drive transistor M1. Terminals Cell1 and Cell2 are connected to both ends of the capacitor C1, and a terminal Out1 is connected to a base of the bypass transistor Q1.
The voltage between both ends of the capacitor C1 (hereinafter referred to as capacitor voltage) is applied to both ends of the voltage setting circuit VS1, and an output VSo1 of the voltage setting circuit VS1 outputs the voltage proportional to the capacitor voltage, and a proportional constant is set by a control circuit (not shown).
The comparator CMP12 compares the output VSo1 of the voltage setting circuit VS1 and the reference voltage Vr1, and the comparator CMP12 outputs a high level when the output VSo1 becomes larger than the reference voltage Vr1. Therefore, when the capacitor C1 is charged to increase the capacitor voltage, the output VSo1 is increased with increasing capacitor voltage, and the output VSo1 reaches the reference voltage Vr1 when the capacitor voltage reaches a certain value. When the output VSo1 becomes the reference voltage Vr1, the output of the comparator CMP12 is switched to the high level to turn on the bypass drive transistor M1 (output control circuit OC1 is brought into conduction when ENIN1 is active). When the bypass drive transistor M1 is turned on, the bypass transistor Q1 is turned on to discharge the capacitor C1, and the capacitor voltage is maintained at a certain value.
The comparator CMP11 monitors low voltage caused by over discharge of the capacitor C1, and the comparator CMP11 stops the discharge of the capacitor C1 when the low voltage is generated.
FIG. 2 is a circuit diagram showing a configuration of the voltage setting circuit VS1. A decoder DeC sets one of outputs OUT1 to OUT16 to the high level according to 4-bit inputs RC1a to RC1d (RC1 of FIG. 1) while setting other output to the low level. Outputs OUT1B to OUT16B have opposite levels to the outputs OUT1 to OUT16 respectively. Voltage dividing resistors r0, r1, . . . , and r18 are connected in series, and an upper end of the resistor r0 is connected to a terminal Cell1, and a lower end of the resistor r18 is connected to a terminal Cell2 through NMOS transistor M1a. The voltage between the terminals Cell1 and Cell2 is the voltage at the capacitor C1.
In analog switches (formed by NMOS transistors and PMOS transistors) ASW1 to ASW15, control terminals ASG are connected to outputs OUT1 to OUT15 of the decoder DeC and control terminals ASGB are connected to outputs OUT1B to OUT15B of the decoder DeC respectively. Terminals IN of the analog switches ASW1 to ASW15 are connected to a midpoint between the resistors r0 and r1, and terminals OUT are connected to a midpoint between the resistors r1 and r2, a midpoint between the resistors r2 and r3, . . . , and a midpoint between the resistors r15 and r16. In the analog switch ASW1 to ASW15, when the control terminal ASG is set to the high level while the control terminal ASGB is set to the low level, the terminals IN-OUT are brought in conduction to short-circuit the resistors r1, r1 and r2, . . . , r1 to r15.
Assuming that the fully charging voltage of the capacitor C1 is set to 2.7V, the voltage setting circuit VS1 changes the monitor voltage of the capacitor C1 from 1.3V to 2.7V in 0.1V increment according to the values of the inputs RC1a to RC1d. That is, the monitor voltage becomes 1.3V when the analog switch ASW1 is turned on, the monitor voltage becomes 1.4V when the analog switch ASW2 is turned on, the monitor voltage is increased by 0.1V by sequentially switching the turn-on of the analog switches ASW3 to ASW14, and the monitor voltage becomes the fully charging voltage of 2.7V when the analog switch ASW15 is turned on.
Because absolute accuracy is required for the monitor voltage of the capacitor C1, the monitor voltage can be changed by trimming a fuse element F1 connected in parallel with the resistor r16. An inverter INV1, an analog switch ASW16, and a resistor r17 perform hysteresis operation of the comparator CMP12.
In the monitor voltage producing circuit, in starting the charging, the analog switches ASW1 of the parallel monitor circuits PM1, PM2, . . . are turned on, and the monitor voltage is set to 1.3V to charge the capacitors C1, C2, . . . . Because the bypass transistor is turned on to perform the discharge in the capacitor which reaches 1.3V, the capacitor is maintained at the monitor voltage of 1.3V. When the control circuit detects that the capacitor voltages of all the capacitors C1, C2, . . . reach 1.3V, the control circuit changes the voltage of the inputs RC1a to RC1d to turn on the analog switches ASW2 of the parallel monitor circuits PM1, PM2, . . . , and the control circuit sets the monitor voltage to 1.4V to charge the capacitors C1, C2, . . . . Because the bypass transistor is turned on to perform the discharge in the capacitor which reaches 1.4, the capacitor is maintained at the monitor voltage of 1.4V. When the control circuit detects that the capacitor voltages of all the capacitors C1, C2, . . . reach 1.4V, the control circuit increases the monitor voltage to 1.5V. Thus, the capacitor voltage is boosted up to the fully charging voltage of 2.7V in 0.1V increment while the capacitor voltage of the plural capacitors C1, C2, . . . are uniformized so as to become the same monitor voltage. Therefore, according to the monitor voltage producing circuit, the charging levels of the plural capacitors C1, C2, . . . can be uniformized when the charging is completed.
Because the capacitor voltage is sequentially boosted while the charging voltages of the electrical double layer capacitors are uniformized, it is necessary that the monitor voltages be boosted at equal intervals. However, in the monitor voltage producing circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155, because the monitor voltage is adjusted on a voltage divider side, the voltage dividing resistors r0 to r15 cannot be uniformized to the same resistance value, but the resistors r0 to r15 have the different resistance values. In order to enhance relative pair accuracy of the resistors in a semiconductor integrated circuit, it is necessary to uniformized shapes, widths, and lengths of the resistors. However, because the resistors r0 to r15 have the different resistance values, unfortunately a variation in accuracy of the resistance value is increased to hardly obtain the accurate monitor voltage.
Additionally, in the monitor voltage producing circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155, it takes a lot of trouble with resistor production because the voltage dividing resistors r0 to r18 are required in each parallel monitor circuit, and it is difficult to produce the resistor because the resistance values are uniformized among the parallel monitor circuits. Therefore, in the structure disclosed in Japanese patent Publication Laid-Open No. 2005-287155, a yield of the monitor voltage producing circuit or parallel monitor circuit is decreased.
A paragraph No. 0025 of Japanese patent Publication Laid-Open No. 2005-287155 describes that “when the resistance values of the resistors r1 to r15 are set to the same resistance value, the difference in voltage between the adjacent monitor voltages set by turning on and off the analog switches ASW1 to ASW15 can be uniformized. For example, the monitor voltage can be set from 1.3V to 2.7V in 0.1V increment.” However, the voltage setting circuit is configured such that the resistors r1 to rn (n=1 to 15) are short-circuited by the analog switches ASW1 to ASW15, the monitor voltages are not changed at equal intervals when the resistance values of the resistors r1 to r15 are equalized, and the resistance values of the resistors r1 to r15 differ from one another when the monitor voltages are changed at equal intervals (for example, 0.4V increment). That is, assuming that the monitor voltages are set to Vm1, Vm2, . . . , and Vm15 in the ascending order, Vm1, Vm2, . . . , and Vm15 are expressed as follows:
            Vm      ⁢                          ⁢      1        =                  [                  1          +                      r            ⁢                                                  ⁢                          0              /                              (                                                      r                    ⁢                                                                                  ⁢                    2                                    +                                      r                    ⁢                                                                                  ⁢                    3                                    +                  …                  +                                      r                    ⁢                                                                                  ⁢                    18                                                  )                                                    ]            ⁢      Vrl                  Vm      ⁢                          ⁢      2        =                  [                  1          +                      r            ⁢                                                  ⁢                          0              /                              (                                                      r                    ⁢                                                                                  ⁢                    3                                    +                                      r                    ⁢                                                                                  ⁢                    4                                    +                  …                  +                                      r                    ⁢                                                                                  ⁢                    18                                                  )                                                    ]            ⁢      Vrl        …            Vm      ⁢                          ⁢      15        =                  [                  1          +                      r            ⁢                                                  ⁢                          0              /                              (                                                      r                    ⁢                                                                                  ⁢                    16                                    +                                      r                    ⁢                                                                                  ⁢                    17                                    +                                      r                    ⁢                                                                                  ⁢                    18                                                  )                                                    ]            ⁢      Vr      ⁢                          ⁢      1      In order to change the monitor voltages at equal intervals, it is necessary to satisfy the following equation:
      r    ⁢                  ⁢          2      /              [                              (                                          r                ⁢                                                                  ⁢                3                            +                              r                ⁢                                                                  ⁢                4                            +              …              +                              r                ⁢                                                                  ⁢                18                                      )                    ⁢                      (                                          r                ⁢                                                                  ⁢                2                            +                              r                ⁢                                                                  ⁢                3                            +              …              +                              r                ⁢                                                                  ⁢                18                                      )                          ]              =            r      ⁢                          ⁢              3        /                  [                                    (                                                r                  ⁢                                                                          ⁢                  4                                +                                  r                  ⁢                                                                          ⁢                  5                                +                …                +                                  r                  ⁢                                                                          ⁢                  18                                            )                        ⁢                          (                                                r                  ⁢                                                                          ⁢                  3                                +                                  r                  ⁢                                                                          ⁢                  4                                +                …                +                                  r                  ⁢                                                                          ⁢                  18                                            )                                ]                    ⁢                          ⁢      …        =          r      ⁢                          ⁢              15        /                  [                                    (                                                r                  ⁢                                                                          ⁢                  16                                +                                  r                  ⁢                                                                          ⁢                  17                                +                                  r                  ⁢                                                                          ⁢                  18                                            )                        ⁢                          (                                                r                  ⁢                                                                          ⁢                  15                                +                                  r                  ⁢                                                                          ⁢                  16                                +                                  r                  ⁢                                                                          ⁢                  17                                +                                  r                  ⁢                                                                          ⁢                  18                                            )                                ]                    The resistors r1 to r15 do not have the same value, but have unique values.
In the monitor voltage producing circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155, because the plural analog switches ASW1 to ASW16 are required in each parallel monitor circuit, the analog switches of the number of parallel monitor circuits×the number of output bits of the decoder are required as a whole, and it is necessary to produce the large number of analog switches. Additionally, the reference voltages Vr1, Vr2, . . . are also required in each parallel monitor circuit. Therefore, in the monitor voltage producing circuit disclosed in Japanese patent Publication Laid-Open No. 2005-287155, the number of components is increased to complicate the structure.
In view of the foregoing, an object of the invention is to provide a capacitor charging control circuit having a simple circuit configuration, in which the voltage divider circuit can be formed by the resistors having an equal resistance value.